The present application relates to a method for monolithic integration of enhancement and depletion-mode heterojunction field effect transistors (“HFETs”) , and in particular, to fabrication of aluminum-gallium nitride/gallium nitride (“AlGaN/GaN”) HFETs using such monolithic integration.
Group III-nitride (“III-N”) compound semiconductors, such as those incorporating AlGaN/GaN, possess the advantages of having wide bandgap, high breakdown field, and large thermal conductivity, which can bring significant benefits to the design of heterostructure field-effect transistors and applications utilizing HFETs. Because of their high power handling capabilities, AlGaN/GaN HFETs can be used for radio frequency/microwave power amplifiers and high power switches. However, most power amplifiers and switches using AlGaN/GaN HFETs feature depletion-mode (“D-mode”) HFETs as the building block. Since a D-mode HFET is a transistor with a negative value for the threshold voltage (Vth), D-mode HFETs need both a positive and negative voltage bias to be turned on and off. If an enhancement-mode (“E-mode”) HFET could be made available, only a positive voltage supply would be needed for circuit applications, resulting in simplified circuits and reduced costs.
Furthermore, owing to the wide bandgap of the GaN-based semiconductor materials, AlGaN/GaN HFETs are capable of high-temperature operation (potentially up to 600° C.), and are thus suitable for high-temperature integrated circuits such as required in aviation and automotive applications. Further, for HFET-based logic circuits, the direct-coupled field effect transistor logic (“DCFL”) features the simplest configuration. In DCFLs, E-mode HFETs are used as drivers while D-mode HFETs are used as the load.
Note that at zero gate bias, a D-mode HFET is capable of conducting current, and is called “normally-on” whereas for an E-mode HFET, the transistor is not conducting current , and is called “normally-off”.
FIG. 1 shows an E-mode HFET 10 using a thin AlGaN barrier layer 12, an undoped GaN layer 18, and a substrate layer 20, such as can be made from sapphire, silicon, or silicon carbide. With the help of the Schottky barrier 14 between the gate metal 16 and the AlGaN barrier, the channel between source 22 and drain 24 can be pinched-off at zero gate bias as long as the AlGaN barrier is thin enough. However, E-mode HFETs fabricated in this manner have poor performance characteristics, such as low transconductance, large on-resistance, and high knee-voltage. This is due to high access resistance. As shown in FIG. 1, the access region between the gate and source also has very low carrier density because of the thin AlGaN barrier. Thus, the access region is also in the E-mode, which needs positive bias to be turned on. To produce E-mode HFETs with low access resistance, a “self-aligned” fabrication process is required, in which only the channel region directly under the gate electrode is in E-mode. Note that gates that are not self-aligned required overlap, which increases device size and stray capacitance.
There have been several attempts at fabrication of E-mode AlGaN/GaN high electron mobility transistors (“HEMTs”). Note that the terms “HEMT” and “HFET” are synonymous. Both are field effect transistors with a junction between two materials with different band gaps, e.g. a heterostructure as the channel. The effect of this heterostructure is to create a very thin layer where the Fermi energy is above the conduction band, giving the channel very low resistance, e.g., “high electron mobility”. As with all the other types of FETs, a voltage applied to the gate alters the conductivity of the thin layer.
Using a thin AlGaN barrier (10 nm), Khan et al. produced an E-mode HEMT with a peak transconductance of 23 mS/mm.
Another attempt to fabricate an E-mode HFET in an AlGaN/GaN system was reported by Hu et al., “Enhancement mode AlGaN/GaN HFET with selectively grown PN junction gate,” April 2000, IEE Electronics Letters, Vol. 36, No. 8, pp. 753-754, which is hereby incorporated by reference in its entirety. In this work a selectively-grown P/N junction gate is used. The selectively-grown P-type layer is able to raise the potential of the channel and therefore deplete the carriers from the channel at zero gate bias. However, such an approach is not self-aligned and the problem of large access resistance persists.
Another attempt to fabricate an E-mode HFET in an AlGaN/GaN system was reported by Moon et al. who used inductively coupled plasma reactive ion etching (“ICP-RIE”) to carry out gate recess-etching. See Jeong S. Moon et al., “Submicron Enhancement-Mode AlGaN/GaN HEMTs,” June 2002, Digest of 60th Device Research Conference, pp. 23-24, which is hereby incorporated by reference in its entirety.
Kumar el at. used a similar approach. Note that the AlGaN barrier under the gate can be thinned by the recess-etching and the threshold voltage is then raised to a positive value. However, ICP-RIE can cause serious damage to the AlGaN barrier and results in increased gate leakage current. To remove ICP-RIE induced damage, the recess-etching patterns must be removed and followed by high-temperature (about 700° C.) annealing. Thus, the gate patterns have to be created again through photo-lithography which cannot be accurately aligned with the recess-etching windows previously generated in the gate recess stage. Therefore, the process requires double photolithography, or alignment, and is not self-aligned. To ensure that the recess windows are fully covered by the gate electrodes, the gate electrodes need to be larger than the recess windows, resulting in a larger gate size, as mentioned earlier. Another problem associated with the ICP-RIE etching is the poor uniformity in the etching depth, which is undesirable for integrated circuits because it severely affects the uniformity in the threshold voltage.
Another approach used gate metals, e.g. Platinum (“Pt”) or Molybdenum (“Mo”), that have larger work function and have the tendency of reacting with III/V compound semiconductors. (Work function refers to the energy required to release an electron as it passes through the surface of a metal.) For example, a Pt-based buried gate technology was previously used in realizing E-mode indium-aluminum-arsenide/indium-gallium-arsenide HFETs. For AlGaN/GaN HFETs, Endoh et al. created an E-mode HFET from a D-mode HFET with a Pt-based gate electrode. Through high temperature gate annealing, the gate metal front can be made to sink into the AlGaN barrier and effectively reduce the barrier thickness and raise the threshold voltage to a positive value. Such an approach requires a D-mode HFET with a threshold voltage already close to zero because the sinking depth of the Pt-gate is limited. However, for monolithically-integrated E/D-mode HFET circuits, it is desirable for the D-mode HFET (which serves as the load) to have a more negative threshold voltage.
U.S. Patent Application 20030218183 entitled “High Power-Low Noise Microwave GaN Heterostructure Field Effect transistor” to Miroslav Micovic et al., discloses a gate recess technique as one existing process technique to fabricate E-mode HFETs. However, in an AlGaN/GaN HFET, because of the lack of effective wet etching techniques, the recess etching is carried out by dry etching. For example, ICP-RIE is used for the recess etching, as mentioned earlier, with the accompanying severe damage and defects to the device.
U.S. Patent Application 2005059197 entitled “Semiconductor Device and Method for Manufacturing the Same” to Yoshimi Yamashita et al., discloses a technique using the approach of using gate metals with larger work function for fabricating E-mode HFETs in GaN-based material systems. However, no metal has been found to have a work function larger than 1 electron volt (“eV”). As a result, in order to fabricate an E-mode HFET using the method of Yamashita et al., a sample which already exhibits a threshold voltage closer to zero volts is needed. This is not suitable for the integration of E-mode and D-mode HEMTs, which are both required for DCFL circuits.
The gate recess technique has also been used to implement monolithic integration of E/D HFETs in AlGaN/GaN heterostructures. As described above, such approach requires a two-mask gate process, introducing extra process steps and cost as compared to a single-mask gate process.
To achieve high density and high-uniformity in the E/D HEMT integration, the three-dimensional mesas impose serious limits to photolithography and interconnects. Thus, a planar process is desired, as seen from the successful development of the commercial GaAs MESFET integrated circuits.
Additionally, due to the lack of P-channel AlGaN/GaN HEMTs, a circuit configuration similar to the based on CMOS cannot be implemented at present. Using N-channel HEMTs, direct-coupled field-effect transistor (“FET”) logic (DCFL), as shown in FIG. 1A, which features integrated enhancement/depletion-mode (“E/D-mode”) HEMTs, offers the simplest circuit configuration.
Because of the heretofore lack of a compatible integration process for both D-mode and E-mode AlGaN/GaN HEMTs. Hussain et al. made a trade-off and used an all-D-mode-HEMT technolgoy and buffered FET logic (“BFL”) configuration to realize an inverter and a 31-stage ring oscillator that includes 217 transistors and two negative voltage supplies.
Based on low damage Cl2-based ICP-RIE technology, Microvic et al. applied the technology of two-step gate recess etching and used plasma-enhanced chemical vapor deposition (“PECVD”)-grown silicon nitride as the gate metal deposition mask to fabricate the E-mode GaN HEMTs, which are integrated with the D-mode GaN HEMT. They showed a propagation delay of 127 ps/stage at a drain bias voltage of 1.2 V for a 31-stage DCFL ring oscillator with the 0.15-μm-gate technology.